Flash storage system and method for accessing a boot program

ABSTRACT

The subject technology relates to a flash storage system for accessing a boot program for a computing system, the flash storage system comprising a flash storage, a random access memory and a flash controller coupled to the flash storage and the random access memory, the flash controller configured to load the boot program from the flash storage into the random access memory. In certain aspects, the flash control is further configured to generate a ready signal indicating the boot program is accessible from the random access memory. Computing systems and methods are also provided.

This application is a continuation of U.S. patent application Ser. No.12/508,528, filed Jul. 23, 2009, and entitled “FLASH STORAGE SYSTEM ANDMETHOD FOR ACCESSING A BOOT PROGRAM,” the entirety of which isincorporated by reference herein.

BACKGROUND

The present invention generally relates to flash storage, and moreparticularly to a flash storage system and method for accessing a bootprogram of a computing system.

A typical computing system executes a boot program upon the occurrenceof a system reset to initialize various devices in the computing system,such as hard drives, floppy drives, and compact disc (CD) drives. Such aboot program is sometimes referred to as a basis input/output system(BIOS). In addition to initializing the various devices in the computingsystem, the boot program may also perform diagnostic self-tests on thedevices to determine whether the devices are operating properly. Thecomputing system then loads one or more software programs, such as anoperating system, from the storage devices into a main memory of thecomputing system and executes the software programs to control operationof the computing system.

In many computing systems, the boot program is stored in a non-volatilememory, such as a read-only-memory (ROM), an erasable read-only-memory(EPROM), or an electrically erasable read-only-memory (EEPROM). Becausethe memory access time of the non-volatile memory is relatively slow,some computing systems load the boot program from the nonvolatile memoryinto a main memory having a faster memory access time. The computingsystem then executes the boot program from the main memory. Loading theboot program from the nonvolatile memory into the main memory, however,consumes processing time and resources in the computing system.Moreover, the boot program consumes memory locations in the main memory,which would otherwise be available for software programs.

In light of the above, a need exists for an improved system and methodfor accessing a boot program.

SUMMARY

In certain implementations the subject technology relates to a flashstorage system for accessing a boot program for a computing system, theflash storage system comprising a flash storage, a random access memoryand a flash controller coupled to the flash storage and the randomaccess memory, the flash controller configured to load the boot programfrom the flash storage into the random access memory. In certainaspects, the flash control is further configured to generate a readysignal indicating the boot program is accessible from the random accessmemory.

In another implementation, the subject technology relates to a computingsystem, comprising a processor, a data memory coupled to the processorand a flash storage device coupled to the processor, the flash storagedevice comprising, a flash storage, a random access memory and a flashcontroller coupled to the flash storage and the random access memory,the flash controller configured to load a boot program from the flashstorage into the random access memory. In certain aspects, the flashcontroller is further configured to generate a ready signal indicatingthe boot program is accessible from the random access memory.

In yet another implementation, the subject technology relates to amethod of accessing a boot program in a computing system comprising aflash storage device, the method comprising, receiving a start signal,loading the boot program from a flash storage of the flash storagedevice to a random access memory of the flash storage device based onthe start signal and generating a ready signal indicating the bootprogram is accessible in the random access memory.

BRIEF DESCRIPTION OF DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention, and together with the description, serve to explain theprinciples of the invention. In the drawings,

FIG. 1 is a block diagram of a computing system including a flashstorage device, in accordance with an embodiment of the presentinvention; and

FIG. 2 is a flow chart of a method of accessing a boot program of acomputing system, in accordance with an embodiment of the presentinvention.

DESCRIPTION

In various embodiments, a flash storage device stores a boot program inflash storage and loads the boot program into a random access memory ofthe flash storage device based on a start signal. Additionally, theflash storage device generates a ready signal indicating the bootprogram is accessible from the random access memory.

FIG. 1 illustrates a computing system 100, in accordance with anembodiment of the present invention. The computing system 100 may be anycomputing or electronic device, such as a computer workstation, anembedded computing system, a network router, a portable computer, apersonal digital assistant, a digital camera, a digital phone, or thelike. The computing system 100 includes a flash storage device 105, adata memory 140, a communication bus 145, a system bus 150, a processor155, and an input/output device 160. The flash storage device 105 andthe processor 155 are coupled in communication with each other throughthe communication bus 145. Additionally, the flash storage device 105,the data memory 140, the processor 155, and the input/output device 160are coupled in communication with each other through the system bus 150.

The data memory 140 may include be any memory, computing device, orsystem capable of storing data. For example, the data memory 140 may bea random access memory (RAM), a dynamic random access memory (DRAM), astatic random access memory (SRAM), a synchronous dynamic random accessmemory (SDRAM), a flash storage, an erasable programmableread-only-memory (EPROM), an electrically erasable programmableread-only-memory (EEPROM), or the like. The processor 155 may include amicroprocessor, a microcontroller, an embedded controller, a logiccircuit, software, firmware, or any kind of processing device. Theinput/output device 160 may include any system or device forcommunicating data with the computing system 100. For example, theinput/output device 160 may include a keyboard, a computer mouse, avideo display, a hard drive, a floppy drive, a compact disc (CD) drive,a read only memory (CD-ROM) drive, a digital versatile disc (DVD) drive,or the like, or any combination thereof.

The flash storage device 105 includes a flash storage 110, a randomaccess memory (RAM) 115, a flash controller 125, a bus interface 130,and a bus interface 135. The flash storage 110 and the random accessmemory 115 are coupled in communication with the flash controller 125.The bus interface 130 is coupled in communication with the random accessmemory 115, the flash controller 125, and the system bus 150. The businterface 135 is coupled in communication with the flash controller 125and the communication bus 145. In some embodiments, the bus interface130 is optional. In these embodiments, the processor 115 is coupled tothe random access memory 115 and the flash controller 125. In someembodiments, the bus interface 135 is optional. In one embodimentwithout the bus interface 135, the processor 135 is coupled to the flashcontroller 125. In another embodiment without the bus interface 135, theprocessor 155 communicates with the flash controller 125 through the businterface 130. In other embodiments, the bus interface 130 or the businterface 135, or both, are external of the flash storage device 105.

The flash storage 110 may be any type of flash storage, such as a flashstorage system, a flash storage device, a flash storage array, or thelike. The flash controller 125 may include a microprocessor, amicrocontroller, an embedded controller, a logic circuit, software,firmware, or any kind of processing device. The random access memory 115may be any type of memory, such as a dynamic random access memory(DRAM), a static random access memory (SRAM), a synchronous dynamicrandom access memory (SDRAM), or the like. In some embodiments, therandom access memory 115 is a dual-port memory. The bus interface 130may be any type of computer or communication interface, such asintegrated drive electronics (IDE) interface. The bus interface 135 maybe any type of computer or communication interface, such as a universalserial bus (UBS) interface, a serial peripheral interface (SPI), amultimedia card (MMC) interface, or a solid-state drive (SD) interface.In some embodiments, the flash storage device 105 has more than oneflash storage 110. In some embodiments, the flash storage device 105 hasmore than one random access memory 115.

The flash storage device 105 also contains a boot program 120 forinitializing the computing system 100. The boot program 120 may be abasic input output system (BIOS), an application level program, anoperating system, or the like. As illustrated in FIG. 1, the flashstorage 110 contains the boot program 120. In various embodiments, theflash controller 125 loads the boot program 120 from the flash storage110 into the random access memory 115. In some embodiments, the flashcontroller 125 is directly coupled to both the flash storage 110 and therandom access memory 115 and directly controls the flash storage 110 andthe random access memory 115 without intervening components, such as anarbiter or a communication interface. In this way, the flash controller125 transfers the boot program 120 from the flash storage device 105 tothe random access memory 115 more quickly than a system that requires anarbiter or a separate communication interface for such a transfer. Insome embodiments, the flash controller 125 performs a direct memoryaccess to transfer the boot program 120 from the flash storage 110 tothe random access memory 115.

The processor 155 accesses the boot program 120 from the random accessmemory 115 and executes the boot program 120. Because the memory accesstime of the random access memory 115 is generally faster than the randomaccess time of the flash storage 110, the processor 155 accesses andexecutes the boot program 120 from the random access memory 115 morequickly than would occur in accessing and executing the boot program 120from the flash storage 110. In this way, execution performance of thecomputing system 100 is improved.

In one embodiment, the flash controller 125 receives a start signal fromthe processor 155, and loads the boot program 120 from the flash storage110 into the random access memory 115 in response to the start signal.For example, the start signal may be a hard system reset signal or asoft system reset signal of the computing system 100. In one embodiment,the flash controller 125 receives the start signal directly from theprocessor 155. In another embodiment, the flash controller 125 receivesthe start signal from the processor 155 through the bus interface 130.In still another embodiment, the flash controller 125 receives the startsignal from the processor 155 through the bus interface 135. In otherembodiments, the flash storage device 105 generates the start signalupon power-on of the flash storage device 105 or receives the startsignal from a device external of the flash storage device 105 uponpower-on of that device. In one embodiment, the device includes acapacitor that charges to a voltage level upon power-on of the computingsystem 100. In this embodiment, the device provides the start signal tothe flash controller 125 when the voltage on the capacitor reaches athreshold voltage.

In a further embodiment, the flash controller 125 provides a readysignal to the processor 155 indicating the boot program 120 isaccessible from the random access memory 115. In one embodiment, theflash controller 125 provides the ready signal directly to the processor155. In another embodiment, the flash controller 125 provides the readysignal to the processor 155 through the bus interface 130. In stillanother embodiment, the flash controller 125 provides the ready signalto the processor 155 through the bus interface 135. In response to theready signal received from the flash controller 125, the processor 155accesses the boot program 120 from the random access memory 115 andexecutes the boot program 120.

In various embodiments, the flash controller 125 loads the boot program120 from the random access memory 115 into the data memory 140 beforeproviding the ready signal to the processor 155. In one embodiment, theflash controller 125 controls operation of the bus interface 130 to loadthe boot program 120 from the random access memory 115 through the businterface 130 and the system bus 150 into the data memory 140. In thisembodiment, the flash controller 125 provides control signals to the businterface 130 for transferring the boot program 120 from the randomaccess memory 115 to the data memory 140. In response to the controlsignals received from the flash controller 125, the bus interface 130obtains access to the system bus 150 and transfers the boot program 120from the random access memory 115 to the data memory 140.

In another embodiment, the flash controller 125 provides a controlsignal to the bus interface 130 for transferring the boot program 120from the random access memory 115 to the data memory 140. In response tothe control signal received from the flash controller 125, the businterface 130 obtains access to the system bus 150 and performs a directmemory access to transfer the boot program 120 from the random accessmemory 115 to the data memory 140. Because the memory access time of therandom access memory 115 is generally faster than the random access timeof the flash storage 110, the bus interface 130 transfers the bootprogram 120 from the flash storage 110 to the data memory 140 morequickly than would occur in transferring the boot program 120 from theflash storage 110 to the data memory 140. In this way, executionperformance of the computing system 100 is improved.

In some embodiments, the size of the boot program 120 is larger than thememory size of the random access memory 115. In this case, the flashcontroller 125 loads the boot program 120 into the data memory 140 bytransferring a portion of the boot program 120 to the random accessmemory 115 and transferring the portion from the random access memory115 to the data memory 140. The flash controller 125 repeats thisprocess until the boot program 120 is contained in the data memory 140and sends the ready signal to the processor 155 indicating the bootprogram 120 is accessible from the data memory 140.

In various embodiments, the flash storage device 105 includes anintegrated circuit containing some or all of the components of the flashstorage device 105. It is to be appreciated that including thecomponents of the flash storage device 105 in an integrated circuitimproves the performance of the flash storage device 105 in contrast toa flash storage device having discrete components because communicationbetween the components of the flash storage device 105 is improved. Forexample, the flash controller 125 may more quickly transfer the bootprogram 120 from the flash storage 110 to the random access memory 115because of higher data transfer rates in the integrated circuit. In oneembodiment, the flash storage device 105 includes a package that ispin-compatible with a DOC-H3 flash storage device available from HynixSemiconductor Inc. of Sunnyvale, Calif. In this embodiment, the flashstorage device 105 includes the functionally of such a DOC-H3 flashstorage device and may be used to replace the DOC-H3 flash storagedevice in various computing systems. In further embodiments, the flashstorage device 105 includes additional functionality than that of theDOC-H3 flash storage device, as is describe more fully herein.

In one embodiment, the processor 155 controls programming of the flashstorage device 105. In this embodiment, the processor 155 communicateswith the flash controller 125 to store or modify the boot program 120 inthe flash storage 110. In another embodiment, an external device, suchas a programmer, may be coupled to the bus interface 135 for storing ormodifying the boot program 120 in the flash storage 110. In stillanother embodiment, the boot program 120 may be initially stored in theflash storage 110 during manufacture of the flash storage device 105.

FIG. 2 illustrates a method 200 of accessing the boot program 120, inaccordance with an embodiment of the present invention. In optional step205, the boot program 120 is loaded into the flash storage 110. In oneembodiment, the boot program 120 is loaded into flash storage 110 duringmanufacture of the flash storage device 105, for example by using aprogrammer to program the flash storage 110. In another embodiment, theprocessor 155 provides the boot program 120 to the flash controller 125,and the flash controller 125 stores the boot program 120 into the flashstorage 110. The method 200 then proceeds to step 210.

In step 210, the flash controller 125 receives a start signal. In someembodiments, the flash controller 125 generates the start signal onpower-up of the flash storage device 105. In other embodiments, theflash controller 125 receives the start signal from the processor 155 orfrom another device external of the flash storage device 105. The method200 then proceeds to step 215.

In step 215, the flash controller 125 loads the boot program 120 fromthe flash storage 110 into the random access memory 115 based on thestart signal. In some embodiments, the flash controller 125 loads theboot program 120 from the flash storage 110 into the random accessmemory 115 in response to the start signal. The method 200 then proceedsto step 220.

In optional step 220, the flash controller 125 loads the boot program120 from the random access memory 115 into the data memory 140. In someembodiments, the flash controller 125 provides a control signal to thebus interface 130, and the bus interface 130 performs a direct memoryaccess in response to the control signal to transfer the boot program120 from the random access memory 115 to the data memory 140. The method200 then proceeds to step 225.

In step 225, the flash controller 125 generates a ready signalindicating that the boot program 120 is accessible by the processor 155.In various embodiments, the flash controller 125 provides the readysignal to the processor 155 directly, though the bus interface 130, orthrough the bus interface 135. In one embodiment, the flash controller125 generates the ready signal indicating the boot program 120 isaccessible from the random access memory 115. In another embodiment, theflash controller 125 generates the ready signal indicating the bootprogram 120 is accessible from the data memory 140. The method 200 thenproceeds to step 230.

In optional step 230, the processor 155 accesses the boot program 120,based on the ready signal received from the flash controller 125.Further, the processor 155 executes the boot program 120 to initializethe computing system 100. In one embodiment, the processor 155 accessesthe boot program 120 from the random access memory 115 in response tothe ready signal received from the flash controller 125. In anotherembodiment, the processor 155 accesses the boot program from the datamemory 140 in response to the ready signal received from the flashcontroller 125. The method 200 then ends.

Although the invention has been described with reference to particularembodiments thereof, it will be apparent to one of ordinary skill in theart that modifications to the described embodiment may be made withoutdeparting from the spirit of the invention. Accordingly, the scope ofthe invention will be defined by the attached claims not by the abovedetailed description.

1. A flash storage system for accessing a boot program for a computingsystem, the flash storage system comprising: a flash storage; a randomaccess memory; and a flash controller coupled to the flash storage andthe random access memory, the flash controller configured to load theboot program from the flash storage into the random access memory, andwherein the flash control is further configured to generate a readysignal indicating the boot program is accessible from the random accessmemory.
 2. The flash storage system of claim 1, wherein the flashcontroller is further configured to load the boot program from the flashstorage into the random access memory in response to a start signal. 3.The flash storage system of claim 2 further configured to generate thestart signal upon a power-on of the flash storage system.
 4. The flashstorage system of claim 1 further comprising an integrated circuitcomprising the flash storage, the random access memory, and the flashcontroller.
 5. The flash storage system of claim 1, wherein the flashcontroller is further configured to load the boot program from the flashstorage into the random access memory by performing a direct memoryaccess.
 6. The flash storage system of claim 1, wherein the flashcontroller is further configured to load the boot program from therandom access memory to a data memory external of the flash storagesystem and to generate a ready signal indicating the boot program isaccessible from the data memory.
 7. The flash storage system of claim 6,wherein the flash controller is further configured to load the bootprogram from the random access memory to the data memory by performing adirect memory access.
 8. The flash storage system of claim 6, whereinthe boot program comprises a basic input-output system.
 9. A computingsystem, comprising: a processor; a data memory coupled to the processor;and a flash storage device coupled to the processor, the flash storagedevice comprising a flash storage; a random access memory; and a flashcontroller coupled to the flash storage and the random access memory,the flash controller configured to load a boot program from the flashstorage into the random access memory, and wherein the flash controlleris further configured to generate a ready signal indicating the bootprogram is accessible from the random access memory.
 10. The computingsystem of claim 9, wherein the flash controller is further configured toload the boot program from the flash storage into the random accessmemory in response to a start signal.
 11. The computing system of claim9, wherein the flash storage device is further configured to generatethe start signal upon a power-on of the flash storage system.
 12. Thecomputing system of claim 9, wherein the processor is further configuredto generate the start signal upon a power-on of the computing system.13. The computing system of claim 9 further comprising an integratedcircuit comprising the flash storage, the random access memory, and theflash controller.
 14. The computing system of claim 9, wherein the flashcontroller is further configured to load the boot program from the flashstorage into the random access memory by performing a direct memoryaccess.
 15. The computing system of claim 9, wherein the flashcontroller is further configured to load the boot program from therandom access memory into the data memory.
 16. The computing system ofclaim 15, wherein the processor is further configured to generate aready signal indicating the boot program is accessible from the datamemory.
 17. The flash storage system of claim 9, wherein the bootprogram comprises a basic input-output system.
 18. A method of accessinga boot program in a computing system comprising a flash storage device,the method comprising: receiving a start signal; loading the bootprogram from a flash storage of the flash storage device to a randomaccess memory of the flash storage device based on the start signal; andgenerating a ready signal indicating the boot program is accessible inthe random access memory.
 19. The method of claim 18 further comprisingloading the boot program into the flash storage.
 20. The method of claim18 further comprising loading the boot program into a data memory of thecomputing system.